On the Power Efficiency, Low latency, and Quality of Service in Network-on-Chip
In multi/many-core System-on-Chips (SoCs), the performance is almost linearly scaling with the number of processing elements.
- Wang, P.
- 12 February 2020
- Thesis in Leiden Repository
In multi/many-core System-on-Chips (SoCs), the performance is almost linearly scaling with the number of processing elements. In order to achieve higher performance, the many-core SoCs have to integrate more processing elements, which results in the communication between processing elements being a bottleneck for the performance improvement. A Network-on-Chip (NoC), with low network latency, high bandwidth, good scalability, and reusability, is promising communication fabric for the many-core SoCs. However, NoCs consume too much power in real chips, which constraints the utilization of NoCs in future large-scale many-core SoC. Meanwhile, with more advanced semiconductor technologies, applied in chip manufacturing, the static power consumption takes a larger proportion of the total power consumption of a NoC. Thus, in this thesis, we have focused our attention on reducing the static power consumption of NoCs in two directions: applying efficient power gating on NoCs to reduce the static power consumption and realizing a confined-interference communication on a simplified NoC infrastructure to achieve energy-efficient packet transmission.