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On the Power Efficiency, Low latency, and Quality of Service in Network-on-Chip

woensdag 12 februari 2020
Rapenburg 73
2311 GJ Leiden


A Network-on-Chip (NoC), with low network latency, high bandwidth, good scalability, and reusability, is promising communication fabric for the many-core System-on-Chips (SoCs). However, NoCs consume too much power in real chips, which constraints the utilization of NoCs in future large-scale many-core SoC. Thus, in this thesis, we reduce the power consumption of NoCs in two directions: applying efficient power gating on NoCs to reduce the static power consumption and realizing a confined-interference communication on a simplified NoC infrastructure to achieve energy-efficient packet transmission.

By powering off the idle components/routers in a NoC, power gating is an effective way to reduce the power consumption of a NoC.
However, power gating causes significant packet latency increase and inefficient power consumption reduction
Thus, to overcome these drawbacks, we have proposed three novel power gating approaches. These power gating approaches are effective in reducing the power consumption of NoCs. Also, with different properties, they have their own advantages.

A confined-interference communication in a NoC-based System-on-Chip is a useful quality-of-service. However, realizing a confined-interference communication on a conventional (virtual channel/buffer based) NoC, a large number of virtual channels are required, which causes high power consumption. To overcome this issue, we have proposed a novel routing approach, called Surfing on a Bufferless NoC (Surf-Bless), which makes it possible for the bufferless NoC to support a confined-interference communication. Furthermore, taking advantage of the low power consumption of the bufferless NoC, our Surf-Bless routing approach is much more power/energy-efficient than the conventional NoC.


  • Dr. T.P. Stefanov
  • Prof.dr. J.N. Kok


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